The present invention relates generally to a data transmission circuit for connecting an output circuit for outputting data to an input circuit to which input data is supplied, and more particularly to a data transmission circuit used in a semiconductor integrated circuit of a data path and a memory, etc.
FIG. 7 is a circuit diagram showing a conventional data transmission circuit.
The data transmission circuit illustrated in FIG. 7 is constructed of an inverter INV and a clocked inverter CKINV that are serially connected between an output circuit 1 for outputting data and an input circuit 2 for receiving data, and an output capacitance Cout connected between an output node a of the inverter INV and a potential node Vss.
Control signals CNT and /CNT (the symbol "/" prefixed to the signal name hereinafter implies a logical inversion) are supplied to the clocked inverter CKINV, whereby the data transmission circuit is switched ON/OFF according to the necessity. The data is thus transmitted between the output circuit 1 and the input circuit 2.
In the conventional data transmission circuit shown in FIG. 7, however, a voltage applied to the node a oscillates at a full amplitude with the data output from the inverter INV, and the electric power consumed in the data transmission circuit is proportional to a square of a voltage amplitude. Accordingly, if an activation rate of the data outputted from the output circuit 1 is high, the problem is that a charging/discharging process at the output capacitance Cout is repeated, which leads to a consumption of large electric power.
Furthermore, the control signal CNT becomes "0", and accordingly the data transmission circuit is switched OFF, at which time an electric potential of an output node b of the clocked inverter CKINV, i.e., the electric potential of an input node b of the input circuit 2 comes to an electric potential between a "1" level signal potential and a "0" level signal potential of the data signal with the result that the node b is brought into a floating state. As a result, a through-current flows between a first power source potential node Vdd and a potential node Vss of an input gate circuit within the input circuit 2, and, because of a multiplicity of data transmission circuits being used in the semiconductor integrated circuit of the data path and the memory etc, this causes an increase in the consumption of the electric power.